Dual-Channel EEG Acquisition Circuit for Vehicular Safety System Based upon Brain-Computer Interface (BCI)

Electroencephalography (EEG) is the basis for many Brain Computer Interface (BCI) applications, where brain waves are captured, filtered, converted to digital form and analysed. In this paper we report on our design and implementation of wide-band dual-channel EEG acquisition circuit that is suitable for various Brain Computer Interface (BCI) applications. The advantages of the designed system include wide bandwidth covering frequencies from 0.2 up to 171 Hz, dual channel, 2 kHz sampling frequency, Analogue-to-Digital Conversion (ADC), simplicity and low cost. The designed EEG acquisition circuit was designed for BCI vehicular safety system, deep sleep and drowsiness detection applications that rely on analysing the lower frequency bands. However, the EEG acquisition circuit offers a wide bandwidth that makes it possible to analyse gamma brain waves that are related to spiritual and high concentration states of the brain. Compared to other EEG acquisition circuits that are limited to 46 and 100 Hz, our design offers greater bandwidth and resolution for high-frequency brain waves, which enables precise analysis of gamma signals. The designed circuit includes level shifter, limiter and ADC, which is driven by Field Programmable Gate Arrays (FPGA). The interface module with FPGA has been accomplished using a Finite State Machine (FSM), which drives the ADC chip and reads digital EEG data into FPGA. The sampling frequency is set at 2 kHz, which enables high grade BCI systems to be realised including clinical applications. Through the use of FPGA, the designed EEG acquisition circuit provides flexible and programmable DSP features, fast processing, accurate timing, stable sampling rate, and low-power consumption. Hardware Description Languages (HDL) such as VHDL and Verilog are the means to program and build various DSP modules inside FPGA.Advanced DSP and control algorithms to be implemented with VHDL/Verilog, simulated and synthesised on FPGA are planned for future work.

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